View PCF8533U_2207419.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet product speci?cation supersedes data of 1999 mar 12 file under integrated circuits, ic12 1999 jul 30 integrated circuits pcf8533 universal lcd driver for low multiplex rates
1999 jul 30 2 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 contents 1 features 2 general description 3 ordering information 4 block diagram 5 pinning 6 functional description 6.1 power-on reset 6.2 lcd bias generator 6.3 lcd voltage selector 6.4 lcd drive mode waveforms 6.4.1 static drive mode 6.4.2 1 : 2 multiplex drive mode 6.4.3 1 : 3 multiplex drive mode 6.4.4 1 : 4 multiplex drive mode 6.5 oscillator 6.5.1 internal clock 6.5.2 external clock 6.6 timing 6.7 display register 6.8 segment outputs 6.9 backplane outputs 6.10 display ram 6.11 data pointer 6.12 subaddress counter 6.13 output bank selector 6.14 input bank selector 6.15 blinker 7 characteristics of the i 2 c-bus 7.1 bit transfer 7.2 start and stop conditions 7.3 system configuration 7.4 acknowledge 7.5 pcf8533 i 2 c-bus controller 7.6 input filters 7.7 i 2 c-bus protocol 7.8 command decoder 7.9 display controller 7.10 cascaded operation 8 limiting values 9 handling 10 dc characteristics 11 ac characteristics 12 bonding pad locations 13 device protection 14 tray information 15 definitions 16 life support applications 17 purchase of philips i 2 c components 18 bare die disclaimer
1999 jul 30 3 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 1 features single-chip lcd controller/driver selectable backplane drive configuration: static or 2/3/4 backplane multiplexing selectable display bias configuration: static, 1 2 or 1 3 internal lcd bias generation with voltage-follower buffers 80 segment drives: up to forty 8-segment numeric characters; up to twentyone 15-segment alphanumeric characters; or any graphics of up to 320 elements 80 4-bit ram for display data storage auto-incremented display data loading across device subaddress boundaries display memory bank switching in static and duplex drive modes versatile blinking modes lcd and logic supplies may be separated wide power supply range: from 1.8 to 5.5 v wide lcd supply range: from 2.5 v for low threshold lcds and up to 6.5 v for guest-host lcds and high threshold (automobile) twisted nematic lcds low power consumption 400 khz i 2 c-bus interface ttl/cmos compatible compatible with 4-bit, 8-bit or 16-bit microprocessors/microcontrollers may be cascaded for large lcd applications (up to 5120 segments possible) no external components compatible with chip-on-glass (cog) technology manufactured in silicon gate cmos process. 2 general description the pcf8533 is a peripheral device which interfaces to almost any liquid crystal display (lcd) with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 80 segments and can easily be cascaded for larger lcd applications. the pcf8533 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). 3 ordering information type number package name description version PCF8533U - chip with bumps in tray -
1999 jul 30 4 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 4 block diagram fig.1 block diagram. handbook, full pagewidth mgl743 lcd voltage selector clock select and timing blinker timebase oscillator input filters i 2 c-bus controller power-on reset clk sync osc scl sda sa0 backplane outputs display control bp0 bp1 bp2 bp3 display segment outputs display register output bank select and blink control 80 s0 to s79 sdaack v dd a0 a1 a2 pcf8533 lcd bias generator v ss v lcd command decode write data control display ram data pointer and auto increment subaddress counter
1999 jul 30 5 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 5 pinning note 1. for most applications sda and sdaack will be shorted together; see chapter 7. 6 functional description the pcf8533 is a versatile peripheral device designed to interface any microprocessor/microcontroller to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 80 segments. the display configurations possible with the pcf8533 depend on the number of active backplane outputs required; a selection of display configurations is given in table 1. all of the display configurations given in table 1 can be implemented in the typical system shown in fig.2. the host microprocessor/microcontroller maintains the 2-line i 2 c-bus communication channel with the pcf8533. the internal oscillator is selected by connecting pad osc to v ss . the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connections required to complete the system are to the power supplies (v dd , v ss and v lcd ) and the lcd panel selected for the application. table 1 selection of display con?gurations symbol pad description sdaack 1 i 2 c-bus acknowledge output; note 1 sda 2 and 3 i 2 c-bus serial data input; note 1 scl 4 and 5 i 2 c-bus serial clock input clk 6 external clock input/output v dd 7 supply voltage sync 8 cascade synchronization input/output osc 9 internal oscillator enable input a0, a1 and a2 10, 11 and 12 subaddress inputs sa0 13 i 2 c-bus slave address input; bit 0 v ss 14 logic ground v lcd 15 lcd supply voltage bp0, bp1, bp2 and bp3 17, 99, 16 and 98 lcd backplane outputs s0 to s79 18 to 97 lcd segment outputs number of 7-segments numeric 14-segments alphanumeric dot matrix backplanes segments digits indicator symbols characters indicator symbols 4 320 40 40 20 40 320 dots (4 80) 3 240 30 30 16 16 240 dots (3 80) 2 160 20 20 10 20 160 dots (2 80) 1 80 10 10 5 10 80 dots (1 80)
1999 jul 30 6 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 fig.2 typical system configuration. handbook, full pagewidth host micro- processor/ micro- controller r t r 2c b sda sdaack scl osc 80 segment drives 4 backplanes lcd panel (up to 320 elements) pcf8533 a0 a1 a2 sa0 v dd v ss v ss v dd v lcd mgl744
1999 jul 30 7 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 6.1 power-on reset at power-on the pcf8533 resets to a starting condition as follows: 1. all backplane outputs are set to v lcd . 2. all segment outputs are set to v lcd . 3. the drive mode 1 : 4 multiplex with 1 3 bias is selected. 4. blinking is switched off. 5. input and output bank selectors are reset (as defined in table 5). 6. the i 2 c-bus interface is initialized. 7. the data pointer and the subaddress counter are cleared. 8. display disabled. data transfers on the i 2 c-bus should be avoided for 1 ms following power-on to allow completion of the reset action. 6.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider of the three series resistors connected between v lcd and v ss . the centre resistor can be switched out of the circuit to provide a 1 2 bias voltage level for the 1 : 2 multiplex configuration. 6.3 lcd voltage selector the lcd voltage selector co-ordinates the multiplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by mode set commands from the command decoder. the biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of v op and the resulting discrimination ratios (d), are given in table 2. a practical value for v op is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10% contrast. in the static drive mode a suitable choice is v op >3v th . multiplex drive ratios of 1 : 3 and 1 : 4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller ( = 1.732 for 1 : 3 multiplex or = 1.528 for 1 : 4 multiplex). the advantage of these modes is a reduction of the lcd full-scale voltage v op as follows: 1 : 3 multiplex ( 1 2 bias): 1 : 4 multiplex ( 1 2 bias): these compare with v op =3v off(rms) when 1 3 bias is used. note: v op =v lcd . 3 21 3 ---------- v op 6v off(rms) 2.449v off(rms) == v op 43 () 3 --------------------- - 2.309v off(rms) = = table 2 preferred lcd drive modes: summary of characteristics lcd drive mode number of lcd bias configuration backplanes levels static 1 2 static 0 1 1:2 2 3 1 2 0.354 0.791 2.236 1:2 2 4 1 3 0.333 0.745 2.236 1:3 3 4 1 3 0.333 0.638 1.915 1:4 4 4 1 3 0.333 0.577 1.732 v off(rms) v op ------------------- v on(rms) v op ------------------- d v on(rms) v off(rms) ------------------- =
1999 jul 30 8 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 6.4 lcd drive mode waveforms 6.4.1 s tatic drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in fig.3. fig.3 static drive mode waveforms. v state1 (t)=v sn (t) - v bp0 (t). v on(rms) =v lcd . v state2 (t)=v sn + 1 (t) - v bp0 (t). v off(rms) =0v. handbook, full pagewidth mgl745 v ss v lcd v ss v lcd v ss v lcd v lcd - v lcd - v lcd v lcd state 1 0 v bp0 s n s n + 1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t frame
1999 jul 30 9 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 6.4.2 1 : 2 multiplex drive mode when two backplanes are provided in the lcd, the 1 : 2 multiplex mode applies. the pcf8533 allows the use of 1 2 bias or 1 3 bias in this mode as shown in figs 4 and 5. fig.4 waveforms for the 1 : 2 multiplex drive mode with 1 2 bias. v state1 (t)=v sn (t) - v bp0 (t). v on(rms) = 0.791v lcd . v state2 (t)=v sn (t) - v bp1 (t). v off(rms) = 0.354v lcd . handbook, full pagewidth mgl746 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd /2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd /2 v lcd /2 v lcd /2 - v lcd - v lcd - v lcd /2 - v lcd /2 s n s n + 1 t frame
1999 jul 30 10 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 fig.5 waveforms for the 1 : 2 multiplex drive mode with 1 3 bias. v state1 (t)=v sn (t) - v bp0 (t). v on(rms) = 0.745v lcd . v state2 (t)=v sn (t) - v bp1 (t). v off(rms) = 0.333v lcd . handbook, full pagewidth mgl747 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd s n s n + 1 t frame v ss v lcd 2v lcd /3 v lcd /3 6.4.3 1 : 3 multiplex drive mode when three backplanes are provided in the lcd, the 1 : 3 multiplex drive mode applies, as shown in fig.6.
1999 jul 30 11 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 fig.6 waveforms for the 1 : 3 multiplex drive mode. v state1 (t)=v sn (t) - v bp0 (t). v on(rms) = 0.638v lcd . v state2 (t)=v sn (t) - v bp1 (t). v off(rms) = 0.333v lcd . handbook, full pagewidth mgl748 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 (a) waveforms at driver. bp2 s n s n + 1 s n + 2 t frame v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd v ss v lcd 2v lcd /3 v lcd /3 6.4.4 1 : 4 multiplex drive mode when four backplanes are provided in the lcd, the 1 : 4 multiplex drive mode applies, as shown in fig.7.
1999 jul 30 12 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 handbook, full pagewidth mgl749 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 s n s n + 1 s n + 2 s n + 3 t frame v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd v ss v lcd 2v lcd /3 v lcd /3 fig.7 waveforms for the 1 : 4 multiplex drive mode. v state1 (t)=v sn (t) - v bp0 (t): v on(rms) = 0.577v lcd . v state2 (t)=v sn (t) - v bp1 (t): v off(rms) = 0.333v lcd .
1999 jul 30 13 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 6.5 oscillator 6.5.1 i nternal clock the internal logic and the lcd drive signals of the pcf8533 are timed either by the built-in oscillator or from an external clock. when the internal oscillator is used, pad osc should be connected to v ss . in this event, the output from pad clk provides the clock signal for cascaded pcf8533s in the system. after power-up, sda must be high to guarantee that the clock starts. 6.5.2 e xternal clock the condition for external clock is made by tying pad osc to v dd ; pad clk then becomes the external clock input. the clock frequency (f clk ) determines the lcd frame frequency. a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state. 6.6 timing the timing of the pcf8533 organizes the internal data flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the synchronization signal ( sync) maintains the correct timing relationship between the pcf8533s in the system. the timing also generates the lcd frame frequency which it derives as an integer division of the clock frequency (see table 3). the frame frequency is a fixed division of the internal clock or of the frequency applied to pad clk when an external clock is used. 6.7 display register the display latch holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship between the data in the display latch, the lcd segment outputs and one column of the display ram. 6.8 segment outputs the lcd drive section includes 80 segment outputs (s0 to s79) which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display latch. when less than 80 segment outputs are required the unused segment outputs should be left open-circuit. 6.9 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which should be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required the unused outputs can be left open-circuit. in the 1 : 3 multiplex drive mode bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. in the 1 : 2 multiplex drive mode bp0 and bp2, bp1 and bp3 respectively carry the same signals and may also be paired to increase the drive capabilities. in the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.10 display ram the display ram is a static 80 4-bit ram which stores lcd data. a logic 1 in the ram bit map indicates the on-state of the corresponding lcd segment; similarly, a logic 0 indicates the off-state. there is a one-to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. the first ram column corresponds to the 80 segments operated with respect to backplane bp0 (see fig.8). in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with bp1, bp2 and bp3 respectively.
1999 jul 30 14 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 when display data is transmitted to the pcf8533 the display bytes received are stored in the display ram in accordance with the selected lcd drive mode. the data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. depending on the current mux mode data is stored singularly, in pairs, triplets or quadruplets. e.g. in 1 : 2 mux mode the ram data is stored every second bit. to illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in fig.9; the ram filling organization depicted applies equally to other lcd types. with reference to fig.9, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display ram addresses. in the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display ram addresses. in the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. this last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. in the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display ram addresses. table 3 lcd frame frequencies frame frequency nominal frame frequency (hz) 64 f clk 24 ---------- - fig.8 display ram bit map showing direct relationship between display ram addresses and segment outputs, and between bits in a ram word and backplane outputs. h andbook, full pagewidth 0 0 1 2 3 1234 7576777879 display ram addresses (rows) / segment outputs (s) display ram bits (columns) / backplane outputs (bp) mgl750
1999 jul 30 15 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 6.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the data pointer by the load data pointer command. following this, an arriving data byte is stored starting at the display ram address indicated by the data pointer thereby observing the filling order shown in fig.9. the data pointer is automatically incremented in accordance with the chosen lcd configuration. that is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode), by three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex drive mode). if an i 2 c-bus data access is terminated early then the state of the data pointer will be unknown. the data pointer should be re-written prior to further ram accesses. 6.12 subaddress counter the storage of display data is conditioned by the contents of the subaddress counter. storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to a0, a1 and a2. the subaddress counter value is defined by the device select command. if the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. the subaddress counter is also incremented when the data pointer overflows. the storage arrangements described lead to extremely efficient data loading in cascaded applications. when a series of display bytes are sent to the display ram, automatic wrap-over to the next pcf8533 occurs when the last ram address is exceeded. subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 27th display data byte transmitted in 1 : 3 multiplex mode). the hardware subaddress should not be changed whilst the device is being accessed on the i 2 c-bus interface. 6.13 output bank selector the output bank selector selects one of the four bits per display ram address for transfer to the display latch. the actual bit selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. in 1 : 4 multiplex, all ram addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. in 1 : 2 multiplex, bits 0 and 1 are selected and, in the static mode, bit 0 is selected. the sync signal will reset these sequences to the following starting points; bit 3 for 1 : 4 multiplex, bit 2 for 1 : 3 multiplex, bit 1 for 1 : 2 multiplex and bit 0 for static mode. the pcf8533 includes a ram bank switching feature in the static and 1 : 2 multiplex drive modes. in the static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. in the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 6.14 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive mode by using
1999 jul 30 16 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 the bank select command. the input bank selector functions independently to the output bank selector. 6.15 blinker the display blinking capabilities of the pcf8533 are very versatile. the whole display can be blinked at frequencies selected by the blink command. the blinking frequencies are integer multiples of the clock frequency. the ratios between the clock and blinking frequencies depend on the mode in which the device is operating, see table 4. an additional feature is for an arbitrary selection of lcd segments to be blinked. this applies to the static and 1 : 2 lcd drive modes and can be implemented without any communication overheads. by means of the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blinking frequency. this mode can also be specified by the blink command. in the 1 : 3 and 1 : 4 multiplex modes, where no alternate ram bank is available, groups of lcd segments can be blinked by selectively changing the display ram data at fixed time intervals. if the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode set command. table 4 blinking frequencies blinking mode normal operating mode ratio nominal blinking frequency off - blinking off 2hz 2hz 1hz 1hz 0.5 hz 0.5 hz f clk 768 ---------- - f clk 1536 ------------ - f clk 3072 ------------ -
1999 jul 30 17 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgl751 s 2 n s 1 n s 7 n s n s n s 3 n s 5 n s 2 n s 3 n s 1 n s 1 n s 1 n s 2 n s n s 6 n s n s 4 n dp dp dp dp a f b g e c d a f b g e c d a f b g e c d a f b g e c d bp0 bp0 bp0 bp1 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n1 n2 n3 n4 n5 n6 n7 bit/ bp n a b x x 0 1 2 3 f g x x e c x x d dp x x n1 n2 n3 bit/ bp n b dp c x 0 1 2 3 a d g x f e x x n1 n2 bit/ bp n a c b dp 0 1 2 3 f e g d n1 bit/ bp cbaf geddp abf gecddp bdpcadgf e ac bdpf egd msb lsb msb lsb msb lsb msb lsb drive mode static 1 : 2 multiplex 1 : 3 multiplex 1 : 4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte fig.9 relationships between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c-bus. x = data bit unchanged.
1999 jul 30 18 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 7 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. by connecting sdaack to sda on the pcf8533, the sda line becomes fully i 2 c-bus compatible. having the acknowledge output separated from the serial data line is advantageous in chip-on-glass (cog) applications. in cog applications where the track resistance from the sdaack pad to the system sda line can be significant, a potential divider is generated by the bus pull-up resistor and the indium tin oxide (ito) track resistance. it is possible that during the acknowledge cycle the pcf8533 will not be able to create a valid logic 0 level. by splitting the sda input from the output the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the sdaack pad to the system sda line to guarantee a valid low level. the following definition assumes sda and sdaack are connected and refers to the pair as sda. 7.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. bit transfer is illustrated in fig.10. 7.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). the start and stop conditions are illustrated in fig.11. 7.3 system con?guration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. the system configuration is illustrated in fig.12. 7.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in fig.13. 7.5 pcf8533 i 2 c-bus controller the pcf8533 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pcf8533 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferred command data and on the hardware subaddress. in single device application, the hardware subaddress inputs a0, a1 and a2 are normally tied to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1 and a2 are tied to v ss or v dd in accordance with a binary coding scheme such that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 7.6 input ?lters to enhance noise immunity in electrically adverse environments, rc low-pass filters are provided on the sda and scl lines.
1999 jul 30 19 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 7.7 i 2 c-bus protocol two i 2 c-bus slave addresses (01110000 and 01110010) are reserved for the pcf8533. the least significant bit of the slave address that a pcf8533 will respond to is defined by the level tied at its input sa0. the pcf8533 is a write only device and will not respond to a read access. therefore, two types of pcf8533 can be distinguished on the same i 2 c-bus which allows: 1. up to 16 pcf8533s on the same i 2 c-bus for very large lcd applications 2. the use of two types of lcd multiplex on the same i 2 c-bus. the i 2 c-bus protocol is shown in fig.14. the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the two pcf8533 slave addresses available. all pcf8533s with the corresponding sa0 level acknowledge in parallel to the slave address, but all pcf8533s with the alternative sa0 level ignore the whole i 2 c-bus transfer. after acknowledgement, a control byte follows which defines if the next byte is ram or command information. the control byte also defines if the next following byte is a control byte or further ram/command data. in this way it is possible to configure the device then fill the display ram with little overhead. the command bytes and control bytes are also acknowledged by all addressed pcf8533s connected to the bus. the display bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated and the data is directed to the intended pcf8533 device. the acknowledgement after each byte is made only by the (a0, a1 and a2) addressed pcf8533. after the last display byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be issued to restart an i 2 c-bus access. 7.8 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. the five commands available to the pcf8533 are defined in table 5. fig.10 bit transfer. mba607 data line stable; data valid change of data allowed sda scl
1999 jul 30 20 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 fig.11 definition of start and stop conditions. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.12 system configuration. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.13 acknowledgement on the i 2 c-bus. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
1999 jul 30 21 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... examples a) transmit two bytes of ram data mgl752 s a 0 s 01110 0 0 control byte slave address ram/command byte ram data m s b l s b a a p r/w = 0 s a 0 s 01110 0 01 0 a a a p ram data a b) transmit two command bytes command s a 0 s 01110 0 10 0 a a a p command a a c) transmit one command byte and two ram bytes command s a 0 s 01110 0 10 00 01 0 a a a p ram data a ram data a a co rs fig.14 i 2 c-bus protocol. fig.15 format of control byte. co = 0; last control byte. co = 1; control bytes continue. rs = 0; data is a command byte rs = 1; data is a display byte mgl753 unused co rs msb lsb
1999 jul 30 22 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 table 5 de?nition of pcf8533 commands table 6 mode set option 1 table 7 mode set option 2 table 8 mode set option 3 command opcode options description mode set 1 1 0 0 e b m1 m0 table 6 de?nes lcd drive mode table 7 de?nes lcd bias con?guration table 8 de?nes display status; the possibility to disable the display allows implementation of blinking under external control load data pointer 0 p6 p5 p4 p3 p2 p1 p0 table 9 seven bits of immediate data, bits p6 to p0, are transferred to the data pointer to de?ne one of eighty display ram addresses device select 1 1 1 0 0 a2 a1 a0 table 10 three bits of immediate data, bits a0 to a3, are transferred to the subaddress counter to de?ne one of eight hardware subaddresses bank select 1 1 1 1 1 0 i o table 11 de?nes input bank selection (storage of arriving display data) table 12 de?nes output bank selection (retrieval of lcd display data); the bank select command has no effect in 1 : 3 and 1 : 4 multiplex drive modes blink 1 1 1 1 0 a bf 1 bf 0 table 13 de?nes the blinking frequency table 14 selects the blinking mode; normal operation with frequency set by bf1, bf0 or blinking by alternation of display ram banks. alternation blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes lcd drive mode bits drive mode backplane m1 m0 static 1 bp 0 1 1 : 2 mux (2 bp) 1 0 1 : 3 mux (3 bp) 1 1 1 : 4 mux (4 bp) 0 0 lcd bias bit b 1 3 bias 0 1 2 bias 1 display status bit e disabled (blank) 0 enabled 1
1999 jul 30 23 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 table 9 load data pointer option 1 table 10 device select option 1 table 11 bank select option 1 (input) table 12 bank select option 2 (output) table 13 blink option 1 table 14 blink option 2 note 1. normal blinking is assumed when multiplex rates 1 : 3 or 1 : 4 are selected. 7.9 display controller the display controller executes the commands identified by the command decoder. it contains the status registers of the pcf8533 and co-ordinates their effects. the controller is also responsible for loading display data into the display ram as required by the filling order. 7.10 cascaded operation in large display configurations, up to 16 pcf8533s can be distinguished on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1 and a2) and the programmable i 2 c-bus slave address (sa0). when cascaded pcf8533s are synchronized they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other pcf8533s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see fig.16). the sync line is provided to maintain the correct synchronization between all cascaded pcf8533s. this synchronization is guaranteed after the power-on reset. the only time that sync is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when pcf8533s with different sa0 levels are cascaded). sync is organized as an input/output pad; the output selection being realized as an open-drain driver with an internal pull-up resistor. a pcf8533 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. should synchronization in the cascade be lost, it will be restored by the first pcf8533 to assert sync. the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the pcf8533 are shown in fig.17. the contact resistance between the sync pads of cascaded devices must be controlled. if the resistance is too high then the device will not be able to synchronize properly. this is particularly applicable to cog applications. table 15 shows the limiting values for contact resistance. table 15 sync contact resistance description bits 7 bit binary value of 0to79 p6 p5 p4 p3 p2 p1 p0 description bits 3 bit binary value of 0 to 7 a2 a1 a0 static 1 : 2 mux bit i ram bit 0 ram bits 0 and 1 0 ram bit 2 ram bits 2 and 3 1 static 1 : 2 mux bit o ram bit 0 ram bits 0 and 1 0 ram bit 2 ram bits 2 and 3 1 blink frequency bits bf1 bf0 off 0 0 2hz 0 1 1hz 1 0 0.5 hz 1 1 blink mode bit a normal blinking (1) 0 alternation blinking 1 number of devices maximum contact resistance 2 6000 w 3 to 5 2200 w 6 to 10 1200 w 11 to 16 700 w
1999 jul 30 24 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 fig.16 cascaded pcf8533 configuration. handbook, full pagewidth host micro- processor/ micro- controller sda scl clk osc sync 80 segment drives 4 backplanes 80 segment drives lcd panel (up to 5120 elements) pcf8533 a0 a1 a2 sa0 v ss v ss v ss v dd v dd v lcd v lcd v dd v lcd mgl754 sda sdaack sdaack scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 a2 sa0 pcf8533 bp0 to bp3 r t r 2c b
1999 jul 30 25 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 fig.17 synchronization of the cascade for the various pcf8533 drive modes. handbook, full pagewidth t= frame f frame 1 bp0 sync bp1 (1/2 bias) sync bp2 (a) static drive mode. (b) 1 : 2 multiplex drive mode. (c) 1 : 3 multiplex drive mode. (d) 1 : 4 multiplex drive mode. bp3 sync sync bp1 (1/3 bias) mgl755
1999 jul 30 26 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 8 limiting values in accordance with the absolute maximum rating system (iec 134). 9 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.5 +6.5 v i dd supply current - 50 +50 ma v lcd lcd supply voltage v ss - 0.5 +7.5 v i lcd lcd supply current - 50 +50 ma i ss negative supply current - 50 +50 ma v i(n) input voltage on pads sda, scl, clk, sync, sa0, osc and a0 to a2 v ss - 0.5 v dd + 0.5 v v o(n) output voltage on pads s0 to s79 and bp0 to bp3 v ss - 0.5 v lcd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma p tot total power dissipation - 400 mw p/out power dissipation per output - 100 mw t stg storage temperature - 65 +150 c
1999 jul 30 27 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 10 dc characteristics v dd = 1.8 to 5.5 v; v ss =0v;v lcd = 2.5 to 6.5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. lcd outputs are open-circuit; inputs at v ss or v dd ; external clock with 50% duty factor; i 2 c-bus inactive. 2. not tested; given by design. 3. outputs measured one at a time. symbol parameter conditions min. typ. max. unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage 2.5 - 6.5 v i dd supply current f clk = 1536 hz; note 1 - 820 m a i lcd lcd supply current f clk = 1536 hz; note 1 - 24 60 m a logic v il low-level input voltage v ss - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd v i ol1 low-level output current on pads clk and sync v ol = 0.4 v; v dd =5v 1 -- ma i oh1 high-level output current pad clk v oh = 4.6 v; v dd =5v - 1 -- ma i ol2 low-level output current pad sda v ol = 0.4 v; v dd =5v 3 -- ma i l1 leakage current on pads sa0, a0 to a2, clk, sda and scl v i =v dd or v ss - 1 - +1 m a i l2 leakage current pad osc v i =v dd - 1 - +1 m a v por power-on reset voltage level 1.0 1.3 1.6 v c i input capacitance note 2 -- 7pf lcd outputs v bp dc voltage component on pads bp0 to bp3 c bp =35nf - 100 - +100 mv v s dc voltage component on pads s0 to s79 c s =5nf - 100 - +100 mv r bp output resistance at pads bp0 to bp3 v lcd = 5 v; note 3 - 1.5 10 k w r s output resistance at pads s0 to s79 v lcd = 5 v; note 3 - 6.0 13.5 k w
1999 jul 30 28 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 11 ac characteristics v dd = 1.8 to 5.5 v; v ss =0v; v lcd = 2.5 to 6.5 v; t amb = - 40 to + 85 c; unless otherwise speci?ed. notes 1. typical output duty cycle of 50%. 2. all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . symbol parameter conditions min. typ. max. unit f clk oscillator frequency at pad clk v dd = 5 v; note 1 797 1536 3046 hz t clkh input clk high time 130 --m s t clkl input clk low time 130 --m s t d(p)sync sync propagation delay time - 30 - ns t syncl sync low time 1 --m s t d(plcd) driver delays with test loads v lcd =5v -- 30 m s timing characteristics: i 2 c-bus; note 2 f scl scl clock frequency -- 400 khz t buf bus free time between a stop and start 1.3 --m s t hd;sta start condition hold time 0.6 --m s t su;sta set-up time for a repeated start condition 0.6 --m s t low scl low time 1.3 --m s t high scl high time 0.6 --m s t r scl and sda rise time -- 0.3 m s t f scl and sda fall time -- 0.3 m s c b capacitive bus line load -- 400 pf t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 -- ns t su;sto set-up time for stop condition 0.6 --m s t sw tolerable spike width on bus -- 50 ns fig.18 test loads. handbook, full pagewidth mgs120 w 3.3 k w 1.5 k 0.5v dd v dd v ss sda, scl clk 1 nf bp0 to bp3, and s0 to s79 (2%) (2%) w 6.8 v dd sync (2%)
1999 jul 30 29 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 fig.19 driver timing waveforms. handbook, full pagewidth mgl761 0.7v dd 0.3v dd 0.7v dd 0.3v dd 1/ f clk t d(p)(sync) t d(p)(sync) t clkh t clkl sync clk 0.5 v 0.5 v t plcd bp0 to bp3, and s0 to s79 t syncl (v dd = 5 v) fig.20 i 2 c-bus timing waveforms. d book, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
1999 jul 30 30 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 12 bonding pad locations bonding pad locations (dimensions in m m) all x and y coordinates are referenced to centre of chip (see fig.22). symbol pad x y sdaack 1 - 1079.20 - 594.40 sda 2 - 839.20 - 594.40 sda 3 - 759.20 - 594.40 scl 4 - 599.20 - 594.40 scl 5 - 519.20 - 594.40 clk 6 - 414.80 - 594.40 v dd 7 - 284.80 - 594.40 sync 8 +4.20 - 594.40 osc 9 +119.20 - 594.40 a0 10 +249.20 - 594.40 a1 11 +379.20 - 594.40 a2 12 +581.20 - 594.40 sa0 13 +711.20 - 594.40 v ss 14 +841.20 - 594.40 v lcd 15 +1099.60 - 594.40 bp2 16 +1277.60 - 594.40 bp0 17 +1357.60 - 594.40 s0 18 +1437.60 - 594.40 s1 19 +1517.60 - 594.40 s2 20 +1597.60 - 594.40 s3 21 +1677.60 - 594.40 s4 22 +1757.60 - 594.40 s5 23 +1837.60 - 594.40 s6 24 +1917.60 - 594.40 s7 25 +1997.60 - 594.40 s8 26 +2077.60 - 594.40 s9 27 +2157.60 - 594.40 s10 28 +2237.60 - 594.40 s11 29 +2317.60 - 594.40 s12 30 +2357.60 +594.40 s13 31 +2277.60 +594.40 s14 32 +2197.60 +594.40 s15 33 +2117.60 +594.40 s16 34 +2037.60 +594.40 s17 35 +1957.60 +594.40 s18 36 +1877.60 +594.40 s19 37 +1797.60 +594.40 s20 38 +1717.60 +594.40 s21 39 +1637.60 +594.40 s22 40 +1557.60 +594.40 s23 41 +1477.60 +594.40 s24 42 +1317.60 +594.40 s25 43 +1237.60 +594.40 s26 44 +1157.60 +594.40 s27 45 +1077.60 +594.40 s28 46 +997.60 +594.40 s29 47 +917.60 +594.40 s30 48 +837.60 +594.40 s31 49 +757.60 +594.40 s32 50 +677.60 +594.40 s33 51 +597.60 +594.40 s34 52 +437.60 +594.40 s35 53 +357.60 +594.40 s36 54 +277.60 +594.40 s37 55 +197.60 +594.40 s38 56 +117.60 +594.40 s39 57 +37.60 +594.40 s40 58 - 42.40 +594.40 s41 59 - 122.40 +594.40 s42 60 - 202.40 +594.40 s43 61 - 282.40 +594.40 s44 62 - 362.40 +594.40 s45 63 - 442.40 +594.40 s46 64 - 602.40 +594.40 s47 65 - 682.40 +594.40 s48 66 - 762.40 +594.40 s49 67 - 842.40 +594.40 s50 68 - 922.40 +594.40 s51 69 - 1002.40 +594.40 s52 70 - 1082.40 +594.40 s53 71 - 1162.40 +594.40 s54 72 - 1242.40 +594.40 s55 73 - 1322.40 +594.40 s56 74 - 1402.40 +594.40 symbol pad x y
1999 jul 30 31 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 s57 75 - 1562.40 +594.40 s58 76 - 1642.40 +594.40 s59 77 - 1722.40 +594.40 s60 78 - 1802.40 +594.40 s61 79 - 1882.40 +594.40 s62 80 - 1962.40 +594.40 s63 81 - 2042.40 +594.40 s64 82 - 2122.40 +594.40 s65 83 - 2202.40 +594.40 s66 84 - 2282.40 +594.40 s67 85 - 2362.40 +594.40 s68 86 - 2322.40 - 594.40 s69 87 - 2242.40 - 594.40 s70 88 - 2162.40 - 594.40 s71 89 - 2082.40 - 594.40 s72 90 - 2002.40 - 594.40 s73 91 - 1922.40 - 594.40 s74 92 - 1842.40 - 594.40 s75 93 - 1762.40 - 594.40 s76 94 - 1682.40 - 594.40 s77 95 - 1602.40 - 594.40 s78 96 - 1522.40 - 594.40 symbol pad x y note 1. the dummy pads are not tested. s79 97 - 1442.40 - 594.40 bp3 98 - 1362.40 - 594.40 bp1 99 - 1282.40 - 594.40 alignment marks c1 - +2300.5 +55.0 c2 -- 2320.2 +107.0 f -- 2208.3 - 165.4 dummy pads (connected to segments shown; note d1 (s11) +2469.70 - 594.40 d2 (s11) +2549.70 - 594.40 d3 (s12) +2517.60 +594.40 d4 (s12) +2437.60 +594.40 d5 (s67) - 2442.30 +594.40 d6 (s67) - 2522.30 +594.40 d7 (s68) - 2554.40 - 594.40 d8 (s68) - 2474.40 - 594.40 chip corners (pre-sawing) bottom left -- 2695.00 - 750.00 top right - +2695.00 +750.00 symbol pad x y fig.21 alignment markers. handbook, halfpage ref ref ref c2 c1 f mgl756
1999 jul 30 32 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... o k, full pagewidth mgl759 sdaack sda sa0 scl sync clk osc a0 a1 a2 v dd v ss v lcd . . . . . . . . . . . . . . . d3 s67 d5 d6 s68 s79 bp3 s0 s1 s2 s11 d1 d2 bp0 bp2 bp1 d8 d7 d4 s12 . . . pc8533-2 c 2 c 1 f 0, 0 x y fig.22 bonding pad locations. the position of the bonding pads is not to scale. chip dimensions: approximately 5.40 1.51 mm. bump dimensions: 90 50 17.5 m m. wafer thickness: 381 m m.
1999 jul 30 33 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 13 device protection fig.23 device protection diagram. handbook, full pagewidth sa0 v dd v dd v ss v ss v lcd v ss sda mgl760 v ss sdaack v ss scl v ss clk v dd v ss osc v dd v ss sync v dd v ss a0, a1 a2 v dd v ss bp0, bp1, bp2, bp3 v lcd v ss s0 to s79 v lcd v ss
1999 jul 30 34 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 14 tray information fig.24 tray details. handbook, full pagewidth mgl757 d c a x y f e b the dimensions are given in table 16. table 16 dimensions fig.25 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. handbook, halfpage mgl758 pc8533-2 dim. description value a pocket pitch, x direction 7.37 mm b pocket pitch, y direction 3.68 mm c pocket width, x direction 5.50 mm d pocket width, y direction 1.60 mm e tray width, x direction 50.8 mm f tray width, y direction 50.8 mm x no. pockets in x direction 6 y no. pockets in y direction 12
1999 jul 30 35 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8533 15 definitions 16 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 17 purchase of philips i 2 c components 18 bare die disclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there is no post waffle pack testing performed on individual die. although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, philips semiconductors has no control of third party procedures in the handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 67 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 printed in the netherlands 465006/02/pp 36 date of release: 1999 jul 30 document order number: 9397 750 05045

▲Up To Search▲

Price & Availability of PCF8533U

	To Download PCF8533U Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .